1. Field of the Invention
The invention generally relates to integrated circuit technologies, and more particularly to silicon on insulator, electrostatic discharge diodes incorporated in field effect transistor structures.
2. Description of the Related Art
Conventionally, diodes offered in silicon on insulator (SOI) technologies require the use of polysilicon to serve as a self-aligning mask for the anode/cathode and to block silicide formation, preventing shorting between the anode and cathode regions of the device. The standard practice is for the polysilicon gate to remain after processing is completed. However, this approach has two disadvantages; gate oxide breakdown limitations and increased capacitance loading.
An example of a conventional diode structure is illustrated in FIG. 1, wherein the diode is formed on a single area of silicon over a buried oxide insulator 10 over a substrate 5, and in between the shallow trench isolation regions (STI) 15. The polysilicon gate 30 is used to separate the anode and cathode and to provide silicide blocking. The anode connects to the P+ region 20 of the diode, while the cathode connects to the N+ region 27 of the diode. An N− region 25 (often referred to as the n-type body region), which is positioned under the gate 30, separates the P+ 20 and N+ 27 regions from one another. A pair of insulating spacers 40 is attached to the sidewalls of the gate 30, and a layer of silicide 35 is deposited over the upper surfaces of the gate 30, P+ region 20, and N+ region 27.
A typical diode-based ESD protection circuit is provided in FIG. 2, with the diode structures shown in the encircled regions. As shown, the gate of the diode connects to the cathode. Also, an overlap capacitor is formed between the anode diffusion and the gate. During electrostatic discharge (ESD) events, large voltages can develop between the pad and ground, which can lead to gate oxide breakdown. As illustrated in FIG. 2, the diodes are used in the circuit to protect against the Human Body Model/Machine Model (HBM/MM) and Charged Device Model (CDM), which are well-known models of ESD events. resistors may be added in the circuit in order to have the correct output impedance for the desired I/O performance (impedance matching).
U.S. Patent Application No. 2003/0080386 published on May 1, 2003, the complete disclosure of which is herein incorporated by reference, describes creating an ungated SOI diode that has the PN junction formed between lightly doped body implant regions. '386 publication describes using a MOS gate to form the diode as is known in the art for creating an SOI diode. in '386, the P-well and N-well are implanted in separate processing steps and have to be aligned to each other, and the same is true for the P+ and N+ implants in the non-gated diode.
U.S. Pat. No. 6,589,823 issued on Jul. 8, 2003, the complete disclosure of which is herein incorporated by reference, describes adding a backside contact (“plug”) to SOI diodes in order to provide a path for heat dissipation. diode is not created in a self-aligned fashion as implant masks for N+ and P+ must be aligned to each other in separate lithographic steps, and the silicide blocking mask must also be aligned after the implants are complete. suggests that the resistance characteristics of the diode may suffer because the silicide region is not proximate to the diode junction.
Thus, there is an identified need for a process of manufacturing an SOI diode which solves gate oxide breakdown limitations, and includes decreased capacitance loading and optimally reduced on-resistance. While the conventional devices and methods are adequate for the purposes they were designed to solve, there remains a need for a novel method for processing a self-aligning low capacitance SOI ESD diode, which does not include a polysilicon gate in the final diode structure.